Fabrication begins with an epitaxial InGaAs/InP heterostructure and involves flip-chip packaging, removal of the substrate, and backside lithography.
Top side processing includes etching of the collector stripe down to the base layer, evaporation of self-aligned contacts to the base, deposition of a passivating dielectric, etching of via holes and metallization. At this point all the base and collector contacts are connected in a circuit with lines running over the passivating dielectric. The circuit is then covered by another (``interlevel'') dielectric layer and a relatively small number of selected points of the circuit are connected to ``top'' metal pads through a second set of via holes. The top (``communication'') pads may be relatively wide (e.g., greater than or about 100 um). The interlevel dielectric (e.g., polyimyde) may be planarized. No attempt is made at this stage to contact the emitter.
Flip-chip mount; ``consulator'' film. The circuit is then mounted on a ``carrier'' wafer which has a mirror pattern of metallic communication pads. The carrier may be any substrate, including glass, ceramics, etc., but first and foremost a silicon wafer that has already undergone the integrated circuit processing. Connection between communication pads is established with the help of an anisotropically conducting film with electrical properties. The film must provide a short between overlapping contacts and an open circuit otherwise. Such vertically conducting and laterally insulating films, which may be called ``consulators'', can be prepared in a variety of ways. The primary purpose of the consulator, besides providing vertical electrical connections, is to provide a stable mechanical support for the packaged chip -- support that will become crucial when the InP substrate is removed.
The issue of mechanical reliability of packaging is crucial for all contemplated realizations of AP technology. From the mechanical point of view the AP assembly bears similarity to an epitaxially grown lattice-mismatched heterostructure on a patterned substrate. This problem was first considered by [ Luryi and Suhir (1986) ], resulting in a novel epitaxial growth technique, that has been successfully used by a number of research and industrial users. In principle, a perfectly adequate consulator can be provided by the solder-bump technology. One needs an adhesive dielectric that can flow to fill the narrow spacing between the chip and the carrier wafer and then stiffen to provide the necessary mechanical support. Another possible approach is to use the existing packaging technology of anisotropically conductive adhesive films, used in liquid crystal display assemblies. These materials are not intrinsically anisotropic, they conduct in a preferred direction only after having been processed [ Lyons and Dahringer 1993 ].
Substrate removal and back-side processing. It is quite possible to etch the entire InP substrate down, stopping at a 0.1 um InGaAs layer. This step is based on the well-known extreme selectivity between the etch rates for InP and InGaAs in hydrochloric acid solutions. It is essential that the uncovered surface is uniformly flat, adequate for performing a fine line optical lithography. A large hole etched from the substrate side would not do, because there would be problems with focal depth. The emitter contact is then established on the backside by a standard lift-off evaporation of a suitable metal. It is well known that ohmic contacts to n+ InGaAs are good without alloying. No elevated temperature procedures should be contemplated after the chip has been mounted, because of the limited thermal stability that can be expected of a consulator film and the need to preserve the integrity of fully processed Si integrated circuits on the carrier wafer.
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