Active Packaging - Philosophy

Vision and Rationale

The underlying philosophy for active packaging concept is based on certain general principles that flow from our understanding of the current state of microelectronics industry and our vision of its future trends.

Ever since the invention of the transistor and especially after the advent of integrated circuits, semiconductor devices have kept expanding their role in our life. For better or worse our civilization is destined to be based on semiconductors. Transistor circuits entertain us and keep track of our money, they fight our wars and decipher the secret codes of life, and one day, perhaps, they will relieve us from the burden of thinking and making responsible decisions.

Inasmuch as that day has not yet arrived, we have to fend for ourselves. The key to success is a clear vision of where are we heading in these turbulent times.

There are numerous indications that we are at a turning point in the evolution of the giant VLSI industry. For many years the celebrated silicon technology has known a virtually one-dimensional path of development: reducing the minimal size of lithographic features. There is now widespread realization that this path has brought us to the point of diminishing return.

The often quoted Moore's Law -- supposed to express the exponential nature of the VLSI progress -- is in fact slowing down (see, e.g., [ Brenner 1997 ] ). In 1965 when Intel's founder Gordon Moore proclaimed his exponential law, the time constant in that exponent -- corresponding to the doubling of the number of transistors on a manufactured chip -- was once every 12 months. That would be growing by a factor of 1000 every decade. By the mid 1970's when Moore's Law was firmly entrenched, the actual time constant was about 18 months -- and this corresponds to a factor of about 100 every decade. By the end of 1980's this was no longer valid and the actual time constant was about 2 years. The 1994 SIA Road Map assumes a growth of only about factor of 10 between 1997 and 2007 for microprocessors, implying a time constant of 3 years (to be sure, this projection is likely to be further adjusted).

Realization of this hard reality by captains of the industry has led to a noticeable shift of investment from new technologies to software and circuit design within existing technologies. There is certainly no shortage of opinion about these trends. Some, haunted by the specter of the steel industry, believe that the semiconductor industry has matured and the research game is over. Others believe the progress in hardware technology will come back roaring, based on innovative research. We certainly belong to the latter category. However, the innovative research that we anticipate will be markedly different from that we have been witnessing over the past 20-30 years. Instead of shrinking the dimensions of Si devices, or perfecting exotic compound semiconductor technologies, successful researchers will broker marriages between these technologies. There is no doubt that silicon will remain the dominant semiconductor material; teaching new trick to the old dog will be the key to success.

With the above considerations in mind, we focus our consideration on the integration of high-performance electronic and optoelectronic devices and small systems with Si circuits, based on advanced packaging concepts and interconnect technology. It is our vision that future electronic systems will have critical needs in on-chip transformation of the signal power among electrical, optical, and microwave media. Communication between relatively small subsystems on the same chip and interchip communications from chip interior will enable qualitatively new systems.

This point of view has been a common theme echoed by several key speakers at the recent NATO Advanced Research Workshop on Future of Microelectronics: ``Reflections on the Road to Nanotechnology'' (France, July 1995) [ Luryi et al. (eds) 1996 ]. It has been endorsed by other think tanks as well. The US Army Electronics Strategy Planning Workshop (January, 1995) has identified as Extremely High Priority the research thrust in Advanced Electronic and Optoelectronic Materials with the following justification:

``It is anticipated that future Si IC technology will evolve to incorporate ultra-high performance electronic and opto-electronic on-chip elements. These elements will facilitate input-output functions from the chip interior, as well as high-bandwidth intrachip communication. Relatively small Si subsystems (less than 100,000 gates) need to be internally interconnected using minimum-feature rules. To achieve these goals, research needs to be directed toward: (1) advanced packaging concepts; (2) hybrid devices based on mixed compound semiconductor structures on Si; (3) novel device concepts relating to mixed materials architectures; (4) novel very large scale integrated circuit architectures that take advantage of the wide-band communication between parallel subsystems on a Si chip.''

The central concept we intend to pursue is the so-called ``Active Packaging'' (AP); [ Luryi (1994, 1996) ]. The most important applications of AP will be new system architectures. It is anticipated that future ULSI chips will have a ``chessboard'' architecture: relatively small subsystems, internally interconnected at the minimum-feature rules will be communicating to each other over wide-band channels, implemented with different specifications. These channels may be optical infrared waveguides or wide metal runners. Clearly, the implementation of optical interconnects requires incorporation of compound semiconductor elements on silicon chip. However, even if the interconnection is electrical, the wide-band communication requirements will mandate high-power microwave transmitters and low-noise front-end amplifiers at the receiver side. These are precisely the goals that active packaging is called for to accomplish. An attractive immediate application of active packaging is the implementation of millimeter-wave phased antenna arrays on a silicon chip.

We believe that most significant applications of compound semiconductor electronics will be associated with its use in silicon electronics. The logic of industrial evolution will motivate new paths for a qualitative improvement of system components, other than the traditional path of a steady reduction in fine-line feature size. It is generally accepted that as the future systems will be on-chip systems the role of packaging and interconnects will become paramount. This paradigm shift calls for a radical rethinking of entire manufacturing process -- not only at an individual factory level, but at an even deeper level involving dynamic interaction of distinct factories.

The Active packaging and other techniques for hybrid chip manufacturing will not replace the currently prevalent miniaturization trend in VLSI electronics but rather complement this trend, assuming an expanding role in the production of high performing on-chip systems.

Our underlying macroeconomic model of semiconductor manufacturing is very different from the familiar picture seen today. We project the emergence of highly sophisticated silicon foundries that will not be proprietary to any particular system house. Each of these foundries will service a multitude of semiconductor chip designers. The entire manufacturing process in the central foundries will be transparent to customers, who will interact with these foundries through an input/output matrix of specifications. In a sense the central foundries will be a leading-edge version of today's ``low-tech'' facilities like MOSIS which produce silicon integrated circuits to customer designs, albeit at a level that is one or two generations behind the current state of the art. Emergence of the state-of-the-art facilities of this kind is an unavoidable consequence of the slowing down of Moore's law.

How does one make money in the brave new world where similar facilities are available to everybody? The central foundries themselves should be profitable, but they will operate in the environment of shrinking profit margins. In some countries the central foundries will become strategic institutions, governed politically and subsidized by the taxpayer. One can only hope that the resultant distortion of the market will not destroy its rational evolution.

The other profitable enterprise will be a system house that will become the main customer of central Si factories. The expected shift from the commodity chip to custom chip will be accompanied by a new and profound phenomenon: the truly customized proprietary chip itself will become a commodity item. The competitive advantage of successful system manufacturers will flow from their proprietary circuit design -- but also from their proprietary packaging facilities. Herein lies the gist of the vision that animates our proposal. Packaging itself will become an integral part of the fabrication of individual components, rather than merely the final ``wrapping'' step.

Besides the few multibillion dollar central Si facilities there will be a much larger number of smaller AP facilities -- ranging from one or two million dollar shops to ten million dollar factories, and, occasionally, hundred million dollar factories. These ``small'' factories will embody the entrepreneurial spirit that long ago used to be associated with the VLSI manufacturing but recently has slipped away into software business.

Silicon foundries will perform sequences of operations specified by the customer, according to a transparent input/output rule. While the rapid change and ``spontaneity'' becomes more and more the preserve of AP technologies, practiced at the smaller facilities, the central silicon foundries will operate in a relatively steady-state fashion. Compared to the current silicon fabrication facilities, they will be amenable to a much more efficient planning and control.

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