Compiling VHDL files via SpeedWave 7.20

February 04, 1997

 

This document outlines the procedure to compile a VHDL (.VHD) source file using SpeedWave 7.20 for Windows on USB CAD-LAB PCs running under Windows NT 4.0. SpeedWave is Workview Office's VHDL simulator.

 

Setting the Project

 

In the CAD LAB's computers, all your files will be stored in the J:\ drive. Once your .VHD source file is stored in the J:\ drive, you must set the directory as a Workview Office project.

Note: in this document, italic text implies Windows menu options

  1. Launch Workview Project Manager (Start...Programs...Workview Office...Project Manager)
  2. Use the Browse button to open the J:\ directory
  3. Choose the File...Save As command to save the project as "any name you wish".vpj
    Note:
    this identifies the J:\ directory as the active Workview Office project and then saves the settings in the Project Manager. After saving the project you may close the Project Manager. You must set the project before you can open SpeedWave. If you are already running SpeedWave you must exit SpeedWave and close the "NSD" box on the Windows Taskbar. Then restart SpeedWave after setting the project before you can proceed
  4. Launch SpeedWave (Start...Programs...Workview Office...Speed Wave). Ignore the Simulator's warning that pops on the screen as you launch SpeedWave. Press the OK button

Configuring a Project

 

In order to use SpeedWave you must configure a directory to work with it.

  1. Create a Project Design Library
  2. At the Simulator's window, launch VHDL Manager (select the Tools...VHDL Manager command). Select the File...Create Library command. You can use any legal name for both the Project Design Library and the Symbolic Name. The default Project Design Library name is user.lib. It is wise to use the same name for both the Project Design Library and the Symbolic Name. This creates a new directory called user.lib in the J:\ directory. It also adds this directory as a library to the Libraries list in the VHDL Manager
  3. Use the Browse button to open the J:\ directory
  4. Click OK. This inserts J:\USER.LIB In the Library Pathname field
  5. In the Symbolic Name field, enter USER
  6. Click OK
  7. Click on Cancel to close the Create Library dialog box
  8. Add the VHDL simulation libraries to the search order
  9. Add the Project Design Library (your source code) to the library search order
  10. Click on the List User Libs button to display user.lib in the Libraries list.
  11. Select user.lib from the Libraries list
  12. Click on the Add Lib button to move the library to the Project Libraries list.
  13. Set the library search order. The library search order determines what libraries SpeedWave uses during simulation. The Project Design Library must be listed first in the Project Libraries List. To move the Project Design Library to the beginning of the library search order:
  14. Select the user.lib library from the Project Libraries list
  15. Click on the Set Working button
  16. You MUST save all the library search order information into a vsslib.ini file
  17. Choose the File...Save VSSLIB.INI command. The vsslib.ini file must be stored in the same directory that contains your Project Design. The name and location of the current vsslib.ini file appears just below the menus on the VHDL Library Manager

 

Analyzing a VHDL Source File

 

If your project contains a single VHDL source file,

  • Choose the Analyze...File command of the VHDL Library Manager
  • Select your .VHD file from the VHDL Source File Names area of the dialog box
  • Click on the Analyze button
  • This invokes the Analyzer. The progress of the analysis is shown in the output display area of the Simulator's window. Any errors the compiler encounters in your source code will be flagged in this area.

     

    To correct errors in your source code:

  • Close the Analyzer (depress the close button)
  • Select the Simulator's window and open your .VHD source file through the File...Open command
  • You may edit your .VHD source file now. A useful feature to take you to the line you need to correct is Edit...Goto Line. Enter the line number in the GoTo dialog box
  • To compile your code again you may invoke the analyzer in two ways: you may select the Analyze...File command in the VHDL Manager (as we just did) or choose the Tools...Analyze VHDL command in the Simulator's window
  •  

    Loading the VHDL Model into SpeedWave

     

    Once you have successfully analyzed your VHDL source code you can simulate the compiled VHDL model. Before you can simulate the model you must load it into SpeedWave via the VHDL Manager.

     

    This loads the analyzed entity into SpeedWave. Loading the entity also opens the Navigator and opens the source code editor. After loading a model, the VHDL Manager will automatically close.

     

    Using the Watchpoints Dialog Box to Monitor Signal Values

    This function is useful for troubleshooting your program. You may single step your program during execution and monitor signals that you select during simulation.

     

     

    Creating a Waveform Stream

    You create a waveform stream to establish communication with ViewTrace, the waveform viewer. ViewTrace allows you to graphically view the results of your simulation.

     

    There is a SpeedWave on-line tutorial at Start...Programs...Workview Office...Workview Office Getting Started...Tutorials and Training...Accessing the Tutorials...Speedwave/VHDL Tutorial.