Publications of Bradley S. Carlson

Journal Articles:

  1. B.S. Carlson, C.Y.R. Chen and D.S. Meliksetian, ``Transistor Chaining in Static CMOS Functional Cells of Arbitrary Planar Topology,'' Journal of Discrete Applied Mathematics, in press.
  2. M. Kormicki, A. Mahmood, and B. S. Carlson, "Parallel Logic Simulation on a Network of Workstations Using PVM," ACM Transactions on Design Automation of Electronic Systems, in press.
  3. N.W. Lo, B.S. Carlson and D.L. Tao, "Fault Tolerant Algorithms for Broadcasting on the Star Graph Network," IEEE Transactions on Computers, vol. 46, no. 12, pp. 1357-1362, Dec. 1997.
  4. W.L. Baker, A. Mahmood and B.S. Carlson, ``Parallel Event-Driven Logic Simulation Algorithms: A Tutorial and Comparative Evaluation,'' IEE Proceedings-Circuits Devices Systems, vol. 143, no. 4, Aug. 1996.
  5. Y. Hu and B.S. Carlson, ``A Unified Algorithm for the Estimation and Scheduling of Data Flow Graphs,'' Journal of Circuits, Systems and Computers, vol. 6, no. 3, pp. 287-318, 1996.
  6. Q. Wu, C.Y.R. Chen and B.S. Carlson, ``LILA: Layout Generation for Iterative Logic Arrays,'' IEEE Transactions on CAD of ICAS, vol. 14, no. 11, pp. 1359-1369, Nov. 1995.
  7. B.S. Carlson and S.J. Lee, ``Transistor Reordering for the Delay Optimization of CMOS Digital Circuits,'' IEEE Transactions on CAD of ICAS, vol. 14, no. 10, pp. 1183-1192, Oct. 1995.
  8. C.Y.R. Chen, C.Y. Hou and B.S. Carlson, ``A Pre-Processor for Improving Channel Routing by Hierarchical Pin Permutation,'' IEEE Transactions on CAD of ICAS, vol. 14, no. 7, pp. 896-903, July 1995.
  9. B.S. Carlson, C.Y.R. Chen and D.S. Meliksetian, ``Dual Eulerian Properties of Plane Multigraphs,'' SIAM Journal on Discrete Mathematics, vol. 8, no. 1, pp. 33-50, Feb. 1995.
  10. B.S. Carlson, C.Y.R. Chen and U. Singh, ``Optimal Cell Generation for Dual Independent Layout Styles,'' IEEE Transactions on CAD of ICAS, vol. 10, no. 6, pp. 770-782, June 1991.

Refereed Conference Articles:

  1. Z. Zhu and B.S. Carlson, "Analysis and Experimental Results of a CVTL Buffer Design," in Proceedings of the IEEE International ASIC Conference, pp. 151-155, 1998.
  2. Y.F. Liu, N.W. Lo, M. Subbarao, and Bradley S. Carlson, ``Parallel Implementation of a Unified Approach to Image Focus and Defocus Analysis on the Parallel Virtual Machine," Proceedings of SPIE AeroSense Symposium, vol 3387, Apr. 1998.
  3. S.C. Dong and B.S. Carlson, "A 10-bit Pipelined ADC for High Speed, Low Power Applications," in Proceedings of the Asilomar Conference on Signals, Systems and Computers, 1997.
  4. Z. Zhu and B.S. Carlson, "Critical Voltage Transition Logic: An Ultrafast CMOS Logic Family," in Proceedings of the International Conference on Computer Design, pp. 732-737, 1997.
  5. N.W. Lo, B.S. Carlson and D.L. Tao, "Fault-Tolerant Broadcasting Algorithms in Two Dimensional Circuit-Switched Torus Network," in Proceedings of the International Conference on Parallel and Distributed Computing Systems, 1997.
  6. J.J. Niewiadomski and B.S. Carlson, "CMOS Read-Out IC with Op-Amp Pixel Amplifier for Infrared Focal Plane Arrays," in Proceedings of the IEEE International ASIC Conference, pp. 69-73, 1997.
  7. O.R. Lopez-Bonilla and B.S. Carlson, "A Methodology for the Evaluation of Parallel and Distributed Systems," in Proceedings of the International Workshop on Parallel Computation and Scheduling, 1997.
  8. B.S. Carlson, "A VLSI Circuit Design Course for Practitioners and Researchers," in Proceedings of the IEEE International Conference on Microelectronic Systems Education, pp. 9-10, 1997.
  9. S.C. Dong and B.S. Carlson, "10 Bit, 25 MHz, 15 mW CMOS Pipelined Subranging ADC," in Proceedings of the International Symposium on Circuits and Systems, 1997.
  10. M. Kormicki A. Mahmood and B.S. Carlson, ``Parallel Logic Simulation on a Network of Workstations using PVM,'' in Proceedings of the IEEE Symposium on Parallel and Distributed Processing, 1996.
  11. N.W. Lo, B.S. Carlson and D.L. Tao, ``Fault Tolerant Algorithms for Broadcasting on the Star Graph Network,'' in Proceedings of the IEEE Midwest Symposium on Circuits and Systems, 1996.
  12. B.S. Carlson, N.W. Lo, D.L. Tao and Z. Zhu, ``Granularity Experiments for the Adaptive Multiprocessor System,'' in Proceedings of the IEEE Midwest Symposium on Circuits and Systems, 1996.
  13. Z. Zhu and B.S. Carlson, ``Dynamic Circuits for CMOS and BiCMOS Low Power VLSI Design,'' in Proceedings of the Intl. Symposium on Circuits and Systems, 1996.
  14. B.S. Carlson, C.Y.R. Chen and D.S. Meliksetian, ``Transistor Chaining in CMOS Leaf Cells of Planar Topology,'' in Proc. of the Great Lakes Symposium on VLSI, 1996.
  15. H. Hollander, B.S. Carlson and T.D. Bennett, ``Synthesis of SEU-Tolerant Sequential Circuits using Concurrent Error Correction,'' in Proc. of the Fifth Great Lakes Symposium on VLSI, pp. 90-93, 1995.
  16. Y. Hu and B.S. Carlson, ``A Unified Algorithm for Estimation and Scheduling in High Level Synthesis,'' in Proc. of the Intl. Symposium on Circuits and Systems, pp. 1.57-1.60, 1994.
  17. Y. Hu and B.S. Carlson, ``Improved Lower Bounds for Scheduling in High Level Synthesis,'' in Proc. of the Intl. Symposium on Circuits and Systems, pp. 1.293-1.296, 1994.
  18. Y. Hu, A. Ghouse and B.S. Carlson, ``Lower Bounds on the Iteration Time and the Number of Resources for Functional Pipelined Data Flow Graphs,'' in Proc. of the International Conference on Computer Design: VLSI in Computers and Processors, pp. 21-24, 1993.
  19. B.S. Carlson and C.Y.R. Chen, ``Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering,'' in Proc. of the IEEE/ACM Design Automation Conference, pp. 361-366, 1993.
  20. B.S. Carlson and C.Y.R. Chen, ``Dual Independent Layout Generation of Arbitrary Circuit Topologies,'' in Proc. of the Midwest Symposium on Circuits and Systems, pp. 528-531, 1992.
  21. B.S. Carlson and C.Y.R. Chen, ``Effects of Transistor Reordering on the Performance of MOS Digital Circuits,'' in Proc. of the Midwest Symposium on Circuits and Systems, pp. 121-124, 1992.
  22. B.S. Carlson, C.Y.R. Chen and D.S. Meliksetian, ``An Efficient Algorithm for the Identification of Dual Eulerian Graphs and its Application to Cell Layout'', in Proc. of the International Symposium on Circuits and Systems, pp. 2248-2251, May 1992.
  23. B.S. Carlson, C.Y.R. Chen and U. Singh, ``Dual Independent Cell Generation,'' in Proc. of the International Symposium on Circuits and Systems, pp. 1636-1639, May 1990.