ESE318 Digital System Design
Spring 1998
Prof. Brad Carlson
Office: 215 Light Eng.
Phone: 516-632-8474
Hours: 11:30-12:30, 4-5 Tuesday, 2-4 Thursday
Fax: 516-632-8494
Email: bcarlson@eegw.ee.sunysb.edu
Web: http://www.ee.sunysb.edu/~bcarlson/318.html
Text: N. Balabanian and B.S. Carlson, Digital Circuits: Design
Principles, 1998.
Teaching Assistants:
Jung-Lin Pan jpan@eegw.ee.sunysb.edu;
Section 2;
Office: 202 Light Engineering
Office hours: 5-7 pm Monday
Changshik Kim chakim@ic.sunysb.edu;
Section 3;
Office hours: 1-3 pm Friday
Kwang-Il Ko kko@eegw.ee.sunysb.edu;
Section 1;
Office: 208 Light Engineering
Office hours: 3-5 pm Tuesday and Wednesday
Chwan-Yi Shiah cshiah@ic.sunysb.edu;
Section 4;
Office: 208 Light Engineering
Office hours: 3-5 pm Thursday
Volunteer TAs:
none.
Class meeting room: 102 Light Engineering
Class meeting time: 5:30-6:50pm Tuesday and Thursday
Hardware laboratory: 283A Light Engineering
Computer lab: CEAS CAD lab, 112 Old Engineering or EE CAD Lab, 281
Light Engineering
Computer lab hours: To be announced
Class Schedule
| Date | Material, handouts, quizzes |
| 1/22 (R) | Number Representations handouts: Lab 1 (PowerView tutorial) |
| 1/27 (T) | Binary Arithmetic, Codes, Error Detection and Correction Codes |
| 1/29 (R) | Boolean Algebra, Switching Operations and Switching Expressions and Functions handouts: Lab 2 (CADET tutorial, Logic Analyzer Tutorial) |
| 2/3 (T) | Logic Gates, TTL and CMOS, Wired Logic, Quiz
1 handouts: Lab 3 |
| 2/5 (R) | Minterms, Maxterms and Logical Maps, Quiz 2 |
| 2/10 (T) | Logic Minimization handouts: Lab 4 |
| 2/12 (R) | Exam 1 |
| 2/17 (T) | Tabular Method of Logic Minimization handouts: Lab 5 |
| 2/19 (R) | Adder Circuits, Quiz 3 |
| 2/24 (T) | Multiplexers and Decoders handouts: Lab 6 |
| 2/26 (R) | ROM and PLAs, Quiz 4 |
| 3/3 (T) | Flip-Flops handouts: Lab 7 |
| 3/5 (R) | Flip-Flops, Quiz 5 |
| 3/10 (T) | Registers handouts: Lab 8 |
| 3/12 (R) | Exam 2 |
| 3/17 (T) | No class |
| 3/19 (R) | No class |
| 3/24 (T) | Synchronous Machine Design, Timing Methodology handouts: Lab 9 |
| 3/26 (R) | Synchronous Machine Design, Quiz 6 |
| 3/31 (T) | State Assignment handouts: Lab 10 |
| 4/2 (R) | State Equivalence, Quiz 7 |
| 4/7 (T) | Counter Design handouts: Lab 11 |
| 4/9 (R) | Algorithmic State Machines, Quiz 8 |
| 4/14 (T) | Asynchronous Sequential Machines handouts: Lab 12 |
| 4/16 (R) | Exam 3 |
| 4/21 (T) | ABEL and Design using PLDs |
| 4/23 (R) | ABEL and Design using PLDs, Quiz 9 |
| 4/28 (T) | ABEL and Design using PLDs |
| 4/30 (R) | Design of a Simple Microprocessor, Quiz 10 |
| 5/5 (T) | Design of a Simple Microprocessor |
| 5/11 (M) | Final Exam, 3:30-6:30pm, Light Engineering 102 |
Lab Schedule
Monday |
Tuesday |
Thursday | |||
Section 01 9:25-12:25 pm |
Section 03 7:00-10:00 pm |
Section 04 7:00-10:00 pm | |||
Date |
Lab number |
Date |
Lab number |
Date |
Lab number |
1/22 |
no lab | ||||
1/26 |
no lab |
1/27 |
no lab |
1/29 |
1 |
2/2 |
1 |
2/3 |
1 (8-10 pm) |
2/5 |
2 |
2/9 |
2 |
2/10 |
2 |
2/12 |
|
2/16 |
2/17 |
2/19 |
|||
2/23 |
2/24 |
2/26 |
|||
3/2 |
3/3 |
3/5 |
|||
3/9 |
3/10 |
3/12 |
|||
3/16 |
no class |
3/17 |
no class |
3/19 |
no class |
3/23 |
3/24 |
3/26 |
|||
3/30 |
3/31 |
4/2 |
|||
4/6 |
4/7 |
4/9 |
|||
4/13 |
4/14 |
4/16 |
|||
4/20 |
4/21 |
4/23 |
|||
4/27 |
4/28 |
4/30 |
no lab | ||
Feeling
Comfortable with Logic Analyzers
Data Sheets (pdf format)
The requirements for each laboratory will be given to the students one
week before the laboratory is scheduled. The students are required to specify
and verify the design using the software package WorkView or PowerView
from Viewlogic, Inc. The circuits are specified using the schematic capture
tool (Viewdraw) and verified using the simulation tool (Viewsim)
of PowerView. The students must present printed copies of schematics and
simulation results to the teaching assistants at the beginning of the lab
period. During the lab period the student must construct the circuits according
to the schematic specifications and verify their functionality. Before the
end of the lab period the students must present the constructed circuit
to the teaching assistant. A final report, typed using a word processor,
is due one week after the laboratory is scheduled. The PowerView software
is available in the College of Engineering and Applied Science's CAD Lab,
Room 211 Old Engineering. The WorkView software is available in the EE CAD
Lab, Room 281 Light Engineering. You are responsible for learning to use
the operating system and the software with the assistance of tutorials,
class handouts, teaching assistants and the professor. You will begin using
PowerView for lab number 3, and therefore should know how to create and
functionally simulate a schematic by the date lab 2 is scheduled.
Grading
| Quizzes | 16% |
| Exams | 36% |
| Labs | 24% |
| Final Exam | 24% |
Each of the exams (respectively, quizzes, labs) have equal weight. The quizzes will have a duration of ten minutes each and will be given at the end of the class.
The exams will have a duration of the entire class period (i.e., one
hour and twenty minutes). The lowest two grades out of the ten quizzes will
be discarded.
If you have any condition, such as a physical or mental disability, which will make it difficult for you to carry out the work as I have outlined it or which will require extra time on examinations, please notify me in the first two weeks of the course so that we may make appropriate arrangements.